In response to demands for reduced number of components and use of a single power source for audio amplifying circuits in TVs, personal computers, AV receivers, car audio equipment, and the like, class D power amplifiers of single-ended type are used. In general audio amplifying circuits as well as these class D power amplifiers, unpleasant abnormal sound such as so-called popping noise may be generated upon power-on or power-off. To avoid such a problem, various countermeasures have been taken.
FIG. 13 schematically shows a conventional class D power amplifier of single-ended type. Class D power amplifier 300 has an integrated circuit portion 310. Integrated circuit portion 310 is literally interpreted as a portion in which respective electronic elements are integrated, but may be an aggregate of individual components. A signal input terminal 320 thereof receives an analog input signal Sin, which is then sent to a preamplifier 330. Preamplifier 330 outputs an analog signal to a PWM circuit 350. PWM circuit 350 is provided with an integrating circuit for integrating the analog signal, a triangular wave signal generating circuit for generating a triangular wave signal, and a comparator for comparing the integrated analog signal and the triangular wave signal. It should be noted that the term “PWM” is an abbreviation of “Pulse Width Modulation”, which is well known for one having ordinary skills in the art. A method for modulating an analog signal using a triangular wave signal in such a PWM circuit is known as a separately-excited oscillation type PWM method. Apart from the separately-excited oscillation type PWM method, a self-excited oscillation type PWM method is also known, and is different from the separately-excited oscillation type PWM method in that the triangular wave signal can be output from the output side of the integrating amplifier even though no triangular wave signal generating circuit and comparator need to be provided, however, an oscillator and a Schmitt trigger circuit need to be provided, for example. Apart from these PWM methods, a class D power amplifier employing a delta sigma modulation method is also well known.
In FIG. 13, PWM circuit 350 outputs binarized signals P1, P2, which have been converted into a digital form and therefore have two levels, high and low levels. Binarized signals P1, P2 are respectively led to signal leading lines 342 and 344. Binarized signals P1, P2 are so-called PWM signals, and are respectively sent to a first driver 370 and a second driver 380.
First driver 370 and second driver 380 drive power transistors TR1, TR2, respectively. First driver 370 and second driver 380 are referred to as “high-side driver” and “low-side driver”, respectively. Power transistor TR1 and power transistor TR2 are referred to as “high-side transistor” and “low-side transistor”, respectively. These power transistors are connected in cascade, i.e., in series. Power transistor TR1 has a drain electrode supplied with, for example, power source voltage Vcc, and has a source electrode connected to, for example, the drain electrode of power transistor TR2, which has a source electrode connected to ground potential (GND). When power transistors TR1 and TR2 are switched from on to off and from off to on at the same timing, there exists a period during which both the transistors are on. Accordingly, a period needs to be provided during which both the high-side and low-side transistors are off. This period is called “dead time”. The dead time, not shown in the figure, is produced by dead time producing circuits. The dead time producing circuits, not shown in the figure, are provided between PWM circuit 350 and first driver 370 as well as between PWM circuit 350 and second driver 380.
In a general class D power amplifier, a level shift circuit, not shown in the figure, is employed. Such a level shift circuit is prepared to convert an output voltage of the first driver 370 based on the source potential of the high-side transistor, power transistor TR1, into an amplitude voltage to be applied to the gate of power transistor TR1. No level shift circuit is required for second driver 380. It should be appreciated that the dead time producing circuits and the level shift circuit are not described in FIG. 13 because they are little relevant to the technical idea of the present invention.
Power transistors TR1 and TR2 have a common connection point, which is connected to a signal output terminal 390. Signal output terminal 390 is connected to an inductor L1 and a capacitor C1 both constituting a low pass filter. The low pass filter is prepared to demodulate the PWM signal having been sent to signal output terminal 390, into the original analog signal. Inductor L1 constituting the low pass filter has an inductance of, for example, several ten μH, whereas capacitor C1 has a capacitance value of approximately 1 μF. Further, a coupling capacitor C0, provided to cut off a direct-current component, is set to have a capacitance value of several hundred μF to several thousand μF. Inductor L1 and capacitor C1 have a common connection point, i.e., a signal leading line 194, to which one end of a speaker RL is connected. The other end thereof is connected to one end of coupling capacitor C0 via a signal leading line 196. The other end of coupling capacitor C0 is connected to ground potential GND.
FIG. 14(a)-FIG. 14(d) show various signals and various voltages at circuit elements of signal output terminal 390 shown in FIG. 13 and subsequent stages. FIG. 14(a) shows a PWM output signal P390 sent via signal output terminal 390. FIG. 14(b) shows an analog output signal SRL, which is lead to the common connection point of inductor L1 and capacitor C1, i.e., signal leading line 194, and exists at the one end of speaker RL. Analog output signal SRL is generated by inductor L1 and capacitor C1 integrating PWM output signal P390. Analog output signal SRL shown therein has an average voltage of Vcc/2.
FIG. 14(c) schematically shows a signal SC0 at the one end of coupling capacitor C0, i.e., signal leading line 196, when power source voltage is supplied. Signal SC0 thereat charges coupling capacitor C0, which has a relatively capacitance value, so it takes a relatively long time to reach a stable direct current voltage. In particular, in proportional to the capacitance value of coupling capacitor C0, it takes a relatively long time until the voltage therein is converged to a predetermined direct current voltage. It should be noted that a reference character X1 schematically represents a case where coupling capacitor C0 has a relatively small capacitance value whereas a reference character X2 schematically represents a case where coupling capacitor C0 has a relatively large capacitance value.
FIG. 14(d) schematically shows the waveform of a signal between the ends of speaker RL upon supply of power. Namely, FIG. 14(d) shows a transient voltage ΔSRL across speaker RL, and transient voltage ΔSRL corresponds to a difference in voltage between signal leading lines 194 and 196. Transient voltage ΔSRL causes current to flow in speaker RL, resulting in generation of popping noise. The magnitude and duration of transient voltage ΔSRL are proportional to the size of coupling capacitor C0. A reference character Y1 schematically represents a case where coupling capacitor C0 has a relatively small capacitance value, whereas a reference character Y2 schematically represents a case where coupling capacitor C0 has a relative large capacitance value. In order to eliminate such popping noise, there has been conventionally proposed various circuit devices and eliminating methods.
Patent Document 1 (Japanese Patent Laying-Open No. 2006-93764) describes popping noise and pumping phenomenon, and proposes a digital power amplifier capable of preventing occurrence thereof, having a single-end output, and implemented with an inexpensive configuration. Patent Document 1 is intended to prevent occurrence of popping noise upon power-on and power-off.
Patent Document 2 (Japanese Patent Laying-Open No. 2005-217583) discloses a technical idea concerned with a switching amplifier having a PWM pulse generator allowing for soft starting operation. According to Patent Document 2, a reference voltage generating circuit is provided which generates a reference voltage slowly increasing or decreasing in voltage value so as to slowly increase the duty ratio of a PWM pulse train, after supply of power. Based on the reference voltage and triangular wave signal, the pulse width thereof is increased to slowly increase the duty ratio thereof, thereby realizing soft starting operation upon supply of power. In this way, popping noise is prevented from being generated upon abrupt change in DC (direct current) potential of an output of the class D power amplifier. As with Patent Document 1, Patent Document 2 discloses a technical idea for preventing generation of popping noise upon power-on or power-off.
Patent Document 3 (Japanese Patent Laying-Open No. 2007-151098) suggests, for example in FIG. 1, a class D power amplifier with a single-ended output, and suggests a technical idea of preventing popping noise from being generated when the potential of a smoothing capacitor provided at a stage preceding a speaker is abruptly changed upon supply of power. Namely, Patent Document 3 is intended to prevent popping noise by controlling the potential using a PWM signal upon the supply of power and making switching to provide an output different from actual audio signal, whereby the potential of the smoothing capacitor provided at the stage preceding the speaker is controlled to change smoothly. Specifically, there are provided generating means for generating a pulse signal, which is constituted by a plurality of pulses, prior to output of an audio signal, and sending it to the smoothing capacitor provided at the stage preceding the speaker; and switching means for implementing switching between the audio signal and the pulses. The individual pulses are set so that a duty ratio of pulses preceding in time is smaller than that of pulses coming thereafter in time. In other words, the duty ratio for the pulses is slowly increased with passage of time, so the potential of the smoothing capacitor is not changed abruptly. In this way, the potential of the smoothing capacitor can be increased to a desired reference potential. It is reasonable to consider that the desired reference potential herein corresponds to the half of the height of the pulses, i.e., is as large as substantially the half of the power source voltage. Namely, the technical idea suggested by Patent Document 3 is intended to supply the smoothing capacitor with a pseudo PWM signal during a period of time from the moment of supply of power to the moment at which the potential of the smoothing capacitor reaches the half of the power source voltage, i.e., the moment at which the duty ratio thereof reaches 50%, and to supply the smooth capacitor with an actual audio signal once the duty ratio reaches 50%. As such, Patent Document 3 suggests a technical idea concerned with soft starting operation.
Patent Document 4 (Japanese Patent Laying-Open No. 06-152269) discloses a technical idea for reducing distortion of a reproduction signal caused by change in duty ratio of a PWM signal. In order to achieve this, the width of the PWM signal just before driving a load and the width of the PWM signal just after conversion are compared to each other, and the duty ratio thereof is corrected to match with that of the PWM signal just after conversion. In other words, Patent Document 4 is intended to correct change in duty ratio caused by delay or time lag of a switch's operation upon rising or falling of pulses during a period of time from the moment after the PWM conversion to the arrival to the load. The delay or time lag is caused by a driver and a final portion.
Patent Document 5 (Japanese Patent Laying-Open No. 2006-101022) provides a digital amplifier capable of preventing an audio characteristic from being deteriorated due to distortion of pulse waveform in the digital amplifier. In order to achieve this, a pulse width adjusting circuit is provided to adjust the pulse width of a PWM signal, generated by a PWM converter, in accordance with the level of an audio signal to be sent to a speaker.
Patent Document 6 (Japanese Patent Laying-Open No. 2005-123784) discloses a class D power amplifier employing a delta sigma modulation method for reducing noise resulting from switching between stopping and resuming of signal outputting in accordance with an instruction signal for mute-on/off.
FIG. 15 shows respective waveforms of an audio output and a PWM output upon switching from audio mute-off to mute-on, as shown in FIG. 10 of Patent Document 6. FIG. 15 illustrates a principle of generation of popping noise.
FIG. 15(a) schematically shows that an audio signal with a sine waveform is being output to a speaker during mute-off, and also shows noise, such as popping noise, generated at the moment of stopping the audio output upon switching from mute-off to mute-on.
FIG. 15(b) shows a waveform of a PWM output provided from a PWM modulator. FIG. 15(b) shows that during mute-off, the pulse width is changed according to the amplitude of the waveform of the audio output shown in FIG. 15(a) whereas in the mute-on state, the pulse width is changed to correspond to a signal waveform in which the pulse duty ratio is maintained at 50%. In other words, Patent Document 6 indicates that in the mute-off state, the pulse width of the PWM signal is changed with a certain level of correlation (continuity) in accordance with the waveform of the audio signal, whereas when the PWM signal is suddenly changed in waveform to have a duty ratio of 50% upon entering the mute-on state, the pulse width thereof is abruptly and significantly changed, with the result that the correlation (continuity) of changes in pulse width is highly likely to be lost.
Further, Patent Document 6 recites that change in pulse width is large not only when transition is made from the mute-off state to the mute-on state, but also when transition is made from the mute-on state to the mute-off state. It also suggests that noise such as popping noise is likely to be generated when changes in pulse width of the PWM signal are less correlated (continuous).
The present inventors have conducted various experiments to prevent and suppress generation of popping noise, and accordingly found that noise is also likely to be generated when the duty ratio of a PWM signal is around 0% and around 100%, besides the problems disclosed in Patent Documents 1-6.